Embedded Systems Specialist ExaminationStudy guide

Covers the roles of the MCU (microcontroller), the DSP, the general-purpose CPU, and the SoC; the design-philosophy difference between RISC and CISC; the use-case lineup of the ARM Cortex-M/R/A series; and the judgment skill of choosing the optimal processor configuration from an embedded device's requirements (real-time behavior, power consumption, cost, and computational characteristics).

Covers the instruction execution cycle from fetch through write-back; pipelining, which processes multiple instructions in staggered parallel stages; the hazards (data/structural/control hazards) that disrupt a pipeline and branch prediction; and the judgment skill of designing for performance while prioritizing an embedded device's predictability of real-time behavior and responsiveness.

Covers the difference between external and internal interrupts; the vector table used to look up the address of the handling routine when an interrupt occurs; priority and nested interrupts, which arbitrate among multiple interrupts; interrupt latency, the delay from an interrupt occurring to the start of handling; and the design judgment of keeping an ISR (interrupt service routine) short.

Covers clock generation and frequency division via an oscillator and a PLL (phase-locked loop); the timer/counter and PWM output used for time measurement and event generation; and the judgment skill of reliability design using a watchdog timer (WDT), which detects software runaway and triggers an automatic reset.

Covers the trade-offs in the memory hierarchy between fast-but-expensive SRAM and high-capacity DRAM that requires refresh, the relationship between access latency and cost/capacity, and how to choose a memory configuration under the capacity, cost, and power constraints unique to embedded devices.

Covers the two cache-update policies, write-through and write-back, the hit rate that governs performance, the embedded-specific concern of real-time impact (response-time variability caused by cache misses), and the difference between MMU and MPU for protecting address spaces and regions.

Covers the two flagship non-volatile memories that retain data with power removed—NOR flash and NAND flash—and how their uses differ, EEPROM for byte-addressable rewriting, and the embedded-unavoidable write-cycle endurance limit together with wear leveling, the technique that spreads writes to mitigate it.

Covers DMA (direct memory access), which transfers data between memory and a device without CPU involvement to offload the CPU, memory-mapped I/O, which treats a peripheral device's registers as part of the memory address space, and bus arbitration, the contention that arises when multiple bus masters share a bus, along with its conflict with real-time behavior.

Covers what an RTOS (real-time operating system) is designed to prioritize over a general-purpose OS, the kernel's role in task management, scheduling, and interrupt handling, the three-state transition of a task between running, ready, and waiting (including dormant), and how to judge whether an embedded project should adopt an RTOS or can rely on bare-metal (no-RTOS) design.

Covers the difference between priority-based scheduling and round-robin, the rate-monotonic (RM) fixed-priority algorithm and its utilization-bound schedulability test (the Liu & Layland bound), the Earliest Deadline First (EDF) dynamic-priority algorithm, and how the presence or absence of preemption affects responsiveness—together with judging whether a real periodic task set can meet its deadlines.

Covers the difference in purpose between a semaphore and a mutex for mutual exclusion (counting resource management versus exclusive ownership), event flags for signaling that an event occurred, and the difference between a mailbox and a message queue for passing data—together with judging which primitive to choose for a given inter-task coordination scenario.

Covers the mechanism by which priority inversion arises (a high-priority task is blocked waiting for a resource held by a low-priority task, and is further delayed indefinitely by a medium-priority task preempting that low-priority task), the difference between the two remedies—priority inheritance and priority ceiling—and the four conditions for deadlock (including circular wait) along with avoidance strategies.

Covers the design of separating the ISR (interrupt service routine) from a task and delegating time-consuming work to deferred processing, the difference between hard real-time and soft real-time, the factors behind interrupt latency and jitter, and how response-time analysis is used to estimate worst-case response time.

Covers the distinction between combinational circuits, whose output depends only on the current inputs, and sequential circuits, which remember past state; simplifying logic expressions with a Karnaugh map; the flip-flop, which holds state; and the setup time/hold time constraints of clock-synchronous circuits, building judgment for embedded hardware design.

Covers sensors, which convert temperature, acceleration, light, and similar phenomena into electrical signals; actuators (DC motors, stepping motors, servo motors), which convert electrical signals into physical motion; and PWM and H-bridge driving for controlling motor speed and position, building judgment for selecting sensors/actuators to fit requirements.

Covers the resolution and quantization error of AD conversion, which turns an analog signal into a digital value; the sampling theorem (Nyquist theorem) and aliasing, which describe the conditions under which the original signal can be reconstructed correctly; and the low-pass filter (LPF), which removes high-frequency components, building judgment for AD/DA selection in practice.

Compares the electrical and protocol characteristics of the four major serial communication methods—I2C, which connects multiple devices over two wires; SPI, which is high-speed and full-duplex; UART, which is asynchronous (start-stop synchronization); and CAN, which uses differential signaling for automotive use—building judgment for choosing the optimal interface based on requirements.

Covers input circuit design for the general-purpose I/O pin, GPIO (pull-up, open-drain); the address bus/data bus/control bus connecting the CPU to peripheral devices; and the input capture, output compare, and PWM timer functions that handle time measurement and waveform generation, building basic judgment for embedded hardware I/O design.

Covers the roles of the cross compiler, linker, and locator, which generate executable code on a host such as a PC for a target (embedded board); how to choose among ICE, JTAG, SWD, and emulators for debugging directly on the target hardware; and the judgment needed for real-hardware debugging in practice.

Covers the role of device drivers, which abstract hardware register operations and interrupt handling, the bootloader, which brings up the system immediately after power-on, and the failsafe and rollback design needed for OTA (Over-The-Air) updates in the field.

Covers state-transition diagrams/tables for organizing embedded-device behavior, the trade-off between the event-driven approach, which reacts to external input, and the polling approach, which checks state at a fixed interval, and designing for exhaustiveness and exception transitions so no undefined transition is left behind.

Covers the design principle of keeping an ISR (interrupt service routine) short and deferring follow-up work, designing reentrant functions and using a critical section for mutual exclusion, and addressing memory exhaustion and leaks to protect limited stack/heap resources.

Covers BLE (Bluetooth Low Energy) for short-range low-power connections, Wi-Fi for home/office LANs and mesh-capable Zigbee, LPWA (LoRa, NB-IoT, the 920MHz band) linking wide areas at low power, edge computing that processes data near the sensor before aggregating to the cloud, and secure boot guaranteeing startup integrity plus OTA (Over-The-Air) updates in the field.

Covers sleep and deep sleep modes that halt the CPU to cut power, clock gating that stops the clock to idle circuitry, DVFS that dynamically lowers voltage and frequency to match workload, intermittent operation that stays dormant and wakes only to communicate, and, building on all of these, estimating average current and battery life.

Covers IEC61508, the general functional-safety standard for electrical/electronic/programmable-electronic systems, and its automotive counterpart ISO26262, the safety levels SIL and ASIL they define, FMEA/FTA for systematically identifying failure effects, fail-safe (defaulting to a safe state on failure) versus fail-soft (degrading gracefully while continuing to operate), redundancy and majority voting to cover single failures, and PID control for tracking a target value.