2.2Cache & memory protection

Using a cache in an embedded system improves average processing performance, but "fast on average" and "real-time behavior is guaranteed" are two different things. A firmware developer must understand how a cache's update policy affects reliability and performance, and how much a cache miss can make a real-time task's response time vary, before finalizing a design. This section examines the two cache-update policies and the MMU/MPU memory-protection mechanisms through the lens of real-time behavior.

2.2.1Write-through and write-back

• Write-through writes data to both the cache and main memory simultaneously every time the CPU writes. Main memory always holds the latest value, giving high reliability and consistency, but because main memory is written on every access, write performance is lower than write-back.
• Write-back reflects CPU writes only in the cache, and propagates the changes to main memory in a batch only when the corresponding cache line is evicted (replaced). Write performance is high, but there is a window during which main memory and the cache temporarily disagree (main memory holds a stale value), and a power loss or a memory access by another device during that window risks data inconsistency.

2.2.2Hit rate and real-time impact

• The hit rate is the fraction of CPU accesses found (hit) in the cache. A higher hit rate shortens average access time, but the hit rate depends on the program's execution pattern and cache capacity, and is not always constant.
• What matters to a real-time embedded task is not just average access time but the delay from a cache miss—a miss forces a slow access to main memory, causing that task's execution time to vary far more than usual (increased jitter). For interrupt handling or tasks with tight deadlines, this variability itself can be the very thing that breaks real-time behavior.

A firmware developer is investigating a defect in a motor-control embedded system, where a real-time task that reads a sensor value and updates PWM output on a fixed cycle occasionally exceeds its specified deadline. Profiling shows the average execution time comfortably fits within the deadline, but cache misses cluster specifically when a particular branch path is taken, and only then does the resulting slow access to main memory pile up and spike the execution time. This is a classic cache pitfall—"fast on average, yet it breaks real-time behavior"—a problem that watching only the average-based hit rate would miss. The fix is to lock the control loop's frequently referenced code and data in cache (pinning the cache lines so they are never evicted), or to redesign the task's time budget around worst-case execution time (WCET) rather than average execution time. Next, the developer considers whether to use write-through or write-back for writing logs to non-volatile memory. Because logs are written frequently, write-back would be advantageous for performance, but this system carries a risk of unexpected momentary power interruptions, so adopting write-back risks losing not-yet-flushed cached data during such an interruption, corrupting the log in main memory (or non-volatile storage). The appropriate judgment is therefore to prioritize data consistency and reliability over performance and adopt write-through for log writes. The choice of cache policy is thus decided not by "which is faster" but by "whether the use case prioritizes real-time behavior or reliability."

2.2.3Memory protection via MMU and MPU

• An MMU (memory management unit) translates virtual addresses to physical addresses and provides each process with an independent address space. It enables virtual memory and inter-process memory protection, but its address-translation processing cost and hardware footprint are larger and tend to undermine the predictability of interrupt response, so it is often omitted from small MCUs used in hard real-time applications.
• An MPU (memory protection unit) performs no address translation; it is a lightweight protection mechanism that merely sets access permissions (read-only, no-execute, etc.) for fixed physical address ranges. It cannot provide virtual memory, but its processing overhead is small and its response is predictable, so it is commonly adopted in embedded MCUs (such as the Cortex-M class) where real-time behavior matters most.

2.2.4Section summary

• Write-through updates main memory every time (reliable, slower); write-back updates only the cache immediately (fast, but with a temporary inconsistency window)
• A cache miss threatens real-time behavior through response-time variability (jitter), not just average execution time
• MMU provides virtual-address translation and process isolation but is heavy; MPU is lightweight region protection without address translation, suited to real-time MCUs