What's changed: Initial version
2.1Memory hierarchy & access
Covers the trade-offs in the memory hierarchy between fast-but-expensive SRAM and high-capacity DRAM that requires refresh, the relationship between access latency and cost/capacity, and how to choose a memory configuration under the capacity, cost, and power constraints unique to embedded devices.
For an embedded designer, choosing memory is never just a matter of "fast versus slow." A battery-powered sensor node and an always-powered industrial controller may require the same processing performance, yet the optimal memory configuration differs completely between them. This section builds on the trade-offs between the two representative volatile memories, SRAM and DRAM, to develop the judgment needed to configure memory under the embedded-specific constraints of capacity, cost, and power consumption.
2.1.1SRAM versus DRAM characteristics
- SRAM (Static RAM) holds a bit in a flip-flop, so it needs no refresh and offers fast access (low latency), but each bit uses many transistors, so scaling it up to large capacities is costly and power-hungry. It is used for a CPU's cache and other high-speed buffers near the registers.
- DRAM (Dynamic RAM) holds a bit as charge on a capacitor, so periodic refresh operations are mandatory before the charge naturally leaks away. Its structure is simple and each bit occupies a small area, allowing large capacity at low cost, but refresh overhead and row-access (row-selection) delay make it slower to access than SRAM. It is used as an embedded device's main memory.
2.1.2Memory hierarchy and latency
- The memory hierarchy is a structure in which layers closer to the CPU (registers, cache) are faster, smaller, and more expensive, while layers farther away (main memory, secondary storage) are slower, larger, and cheaper. In embedded design, deciding how much data to place at each layer simultaneously governs performance and manufacturing cost.
- Latency is the delay between issuing a memory access request and actually obtaining the data. In a real-time embedded system, variability in latency (jitter) matters just as much as raw performance—a memory that is fast on average but occasionally stalls for a long time can still cause a deadline to be missed.
Most-tested contrast: "SRAM = no refresh needed, fast, small capacity, expensive" versus "DRAM = refresh required, slower, large capacity, cheap". The reverse belief—"DRAM is faster"—is a classic mistake, so organize your understanding around which side of speed versus capacity the presence of refresh actually affects.
A designer of a battery-powered environmental sensor node is deciding how to configure the memory that temporarily buffers acquired sensor readings and the memory that holds the collection-logic program code. The device is designed around intermittent operation (it sleeps most of the time, wakes at fixed intervals to read a sensor value, and immediately sleeps again), and it faces tight constraints on component count and cost. Since the buffer holding sensor readings only needs a capacity of a few hundred bytes, adding an external large-capacity DRAM would be disadvantageous in cost, board area, and power consumption (DRAM's periodic refresh keeps consuming power even while the device is idle), so it is reasonable to rely solely on the MCU's built-in SRAM (a few KB to a few dozen KB). On the other hand, suppose the device has a future plan to add advanced signal processing (noise reduction or data-compression algorithms), and the program code plus working memory is expected to grow beyond a few dozen KB. Then the built-in SRAM alone would run short of capacity, shifting the judgment toward adding external DRAM. Even then, because DRAM demands refresh power even during the sleep periods of intermittent operation, the designer must always estimate the impact on battery life, and consider it together with an additional power-saving design such as "cut power to the DRAM entirely during sleep and reload its contents from external flash on wake-up." Memory-configuration judgment therefore must always weigh not just "the capacity required" but also "the power-consumption profile during intermittent operation."
| Item | SRAM | DRAM |
|---|---|---|
| Refresh | Not required | Required (periodic rewrite) |
| Access speed | Fast | Slower than SRAM |
| Cost/area per bit | High | Low |
| Typical use | Cache, register-adjacent buffers | Main memory |
Trap: "SRAM should always be used where large capacity is needed" is wrong—SRAM's large per-bit area and cost make it unsuited to scaling up, and DRAM is the standard choice for main memory that needs large capacity. Also wrong: "DRAM is a newer memory type that no longer needs refresh"—as long as DRAM relies on a capacitor to hold charge, refresh is fundamentally required (only SRAM and non-volatile memory, covered later, avoid it).
2.1.3Section summary
- SRAM = no refresh, fast, small capacity, expensive; DRAM = refresh required, slower, large capacity, cheap
- The memory hierarchy is faster/smaller/costlier near the CPU and slower/larger/cheaper farther away
- In embedded design, choose the memory configuration by weighing the power-consumption profile during intermittent operation, not just capacity
Sign in to track progress — Log in.
Quick check
(just a quick review)Q1. You are configuring the memory for a few-hundred-byte sensor-value buffer on a battery-powered device with intermittent operation. From a cost, board-area, and power-consumption standpoint, which choice is most appropriate?
Q2. An embedded engineer claims, "DRAM is faster than SRAM, so DRAM should be used for a cache that requires fast access." What is the most accurate rebuttal to this claim?
Q3. In designing an embedded system's memory hierarchy, which characteristic should the memory layer placed closest to the CPU's registers have?