4.1Logic circuits

For an embedded hardware designer, a logic circuit is not a binary "does it work or not" question—it is the task of building a circuit that satisfies both gate count (cost, power) and timing constraints (the maximum clock frequency it can run at). The same logic expression can require a different gate count depending on implementation, and the same flip-flop will malfunction if data arrival timing is off. This section builds two judgment axes grounded in the differing natures of combinational and sequential circuits: simplifying a circuit, and synchronizing it correctly.

4.1.1Combinational versus sequential circuits

• A combinational circuit is built solely from gates such as AND/OR/NOT, and its output is uniquely determined by the current inputs alone, with no memory of past state whatsoever. Adders, decoders, and multiplexers are representative examples; internally, it has no feedback path (wiring that routes its own output back to its own input).
• A sequential circuit adds a memory element (a flip-flop) and a feedback path to a combinational circuit, so that the same input can produce a different output depending on "the current internal state". Counters, registers, and the finite state machines (FSMs) that implement state transitions are representative examples of sequential circuits. Embedded protocol handling and control logic are, at their core, designed as sequential circuits.

4.1.2Simplification with a Karnaugh map

• A Karnaugh map rearranges a truth table into a grid so that cells representing inputs differing by only one bit are placed adjacent to each other, allowing logic-expression simplification to be done visually. Grouping adjacent 1s (outputs that are true) into a power-of-two count (1, 2, 4, 8, ...) simplifies that group into a product term retaining only the variables that do not change across it.
• The benefit of a Karnaugh map is that it directly translates into fewer gates—meaning lower implementation cost and lower power consumption. In embedded devices, where FPGA/ASIC area constraints or an MCU's built-in simple logic (such as generating a GPIO interrupt condition) make gate count feed straight through to cost, the Karnaugh map is used in practice because it is visual and less prone to oversights than purely algebraic simplification (applying Boolean-algebra theorems). Once there are five or more variables, however, the grid becomes unwieldy, and in practice the task is often handed off to tooling (automatic optimization by a logic-synthesis toolchain).

4.1.3Flip-flops and setup/hold time

• A flip-flop (FF) is a memory element holding one bit of state. A D flip-flop captures the value on its D input at a clock edge (rising or falling) and reflects it on the Q output. An RS flip-flop controls state directly via set/reset inputs, and a JK flip-flop is a derivative that resolves the RS flip-flop's forbidden input combination (S = R = 1) by turning it into a "toggle" action instead. Embedded registers, counters, and state storage are, at their core, implemented as collections of D flip-flops.
• Setup time is the minimum duration for which the D input must already hold a stable, settled value immediately before the clock edge arrives. Hold time is the minimum duration for which the D input must remain unchanged and stable immediately after the clock edge arrives. If either constraint is violated, the flip-flop's output can go indeterminate (metastable) or latch the wrong value—a classic cause of an embedded board that "misbehaves intermittently."

Suppose a firmware developer is investigating a defect in which a communication interface circuit implemented on an FPGA occasionally corrupts bits, but only under certain temperature conditions. Simulation has already confirmed the circuit's logic expression (the combinational part) is correct, so the suspect is a setup/hold time violation in the clock-synchronous portion. As temperature rises, signal propagation delay changes (generally increasing with higher temperature), and the transmitting side's combinational-circuit output starts arriving only at a timing that cuts into the setup time relative to the receiving flip-flop's clock edge—this is the true cause of a low-reproducibility defect that "only occurs under certain conditions." There are two ways to address it. The first is to lower the clock frequency, which relatively widens the setup margin against the clock period (at the cost of reduced throughput). The second is to reduce the number of combinational-logic stages to shorten the propagation delay itself, and this is where Karnaugh-map-based logic simplification pays off—fewer gate stages mean less propagation delay, widening the setup-time margin (timing margin) even at the same clock frequency. A common misjudgment here is to assume "bit corruption must be a communication-protocol (parity/CRC, etc.) problem" and look only at the upper layer. Timing violations occur at the lower hardware layer, so revisiting the protocol will not fix a low-reproducibility defect of this kind. A hardware designer investigating a rare malfunction should first consider setup/hold timing analysis (static timing analysis, or STA) as a suspect.

4.1.4Section summary

• A combinational circuit determines output from current inputs alone; a sequential circuit holds internal state via a flip-flop plus feedback
• A Karnaugh map groups adjacent 1s into power-of-two counts to reduce gate count (cost and power consumption)
• Violating setup time (immediately before the edge) or hold time (immediately after the edge) makes an FF's output indeterminate and causes intermittent malfunctions