Embedded Systems Specialist Examination — knowledge map
The 41 core concepts of Embedded Systems Specialist Examination and how they connect. Click a node in the map above to explore related terms and prerequisites; the list below indexes every concept with its definition and links to its prerequisites and related concepts.
Concepts (41)
Critical section
A section of code that accesses a shared resource such that concurrent execution by multiple tasks or interrupt handlers could cause inconsistency (a race condition). Access from elsewhere must be prevented during this section, typically by disabling interrupts or using a mutex, but making the section longer than necessary degrades interrupt responsiveness and task-switch latency, so it should be kept as short as possible.
Prerequisites: Interrupt Service Routine (ISR)、Mutex
Interrupt Service Routine (ISR)
A dedicated handler routine invoked by hardware when an interrupt occurs. Standard design practice keeps its execution time to a minimum for responsiveness, deferring any lengthy processing to a regular task. Calling a non-reentrant function or performing long operations inside an ISR degrades the responsiveness of other interrupts and tasks.
Related: Reentrant
Mutex
A synchronization primitive that lets multiple tasks access a shared resource exclusively. It resembles a binary semaphore (count of 0/1) but differs in having the concept of ownership — only the task that locked it may unlock it — which is what makes priority inheritance protocols applicable. Embedded RTOSes use mutexes to serialize access to shared variables or hardware resources.
Prerequisites: Priority inheritance / priority ceiling protocol、Real-Time OS (RTOS)、Semaphore
Functional safety
The overarching concept — and the set of methods to realize it — of preventing electronic/electrical systems from reaching a hazardous state even when a malfunction or failure occurs, through detection and control mechanisms. It covers both hardware failures and software defects, and defines safety integrity levels (SIL/ASIL) matched to the magnitude of risk, driving design and verification to the required level of reliability.
Related: ISO 26262
Microcontroller (MCU)
A single-chip embedded processor integrating a CPU core, memory (flash/SRAM), and peripheral I/O (timers, UART, ADC, etc.). Compared with a general-purpose CPU plus external memory, it offers lower cost, lower power, and a smaller footprint, making it the default choice for appliances and IoT devices. Selecting the right MCU for performance, power, pin count, and cost is a starting point of embedded design.
Prerequisites: SRAM / DRAM、UART (Universal Asynchronous Receiver/Transmitter)
ARM Cortex series (M/R/A)
A family of ARM processor cores tailored by use case: Cortex-M targets low-power, low-cost microcontroller applications; Cortex-R targets hard-real-time control applications; and Cortex-A targets high-performance, OS-hosting workloads (Linux, Android, etc.). Embedded designers select a series based on real-time requirements, performance needs, and power budget.
Prerequisites: Hard real-time / soft real-time、Microcontroller (MCU)
FMEA (Failure Mode and Effects Analysis)
A bottom-up analysis method that enumerates the possible failure modes of each component and evaluates their effect on the overall system. Because it builds up from individual component failures to system-level impact, it systematically surfaces the consequences of single failures that might otherwise be overlooked during design. It is positioned as a required analysis in the functional-safety design process.
Prerequisites: Functional safety
IEC 61508
The international basic standard for functional safety of electrical/electronic/programmable electronic (E/E/PE) safety-related systems. It is a general-purpose standard applied across industrial equipment, defining Safety Integrity Levels (SIL) 1 through 4 based on risk magnitude, along with requirements for the design process, verification, and failure rates. It underlies industry-specific derivative standards such as ISO 26262 for automotive.
Prerequisites: Functional safety
Related: ISO 26262
Interrupt latency
The time between an interrupt request occurring and the corresponding interrupt service routine (ISR) actually beginning execution. It depends on the length of interrupt-disabled sections and the priority design of nested interrupts. Real-time systems must estimate the worst-case value of this latency to verify that deadlines can be met.
Prerequisites: Interrupt Service Routine (ISR)、Nested interrupt
Real-Time OS (RTOS)
An operating system designed to control task execution order and response time deterministically (predictably), prioritizing adherence to specified deadlines. Whereas general-purpose OSes optimize for throughput and fairness, an RTOS provides priority-based scheduling and short, bounded interrupt response times to satisfy the timing requirements of control systems and communication equipment.
Semaphore
A mechanism for controlling concurrent access to a shared resource by multiple tasks (processes). It uses a counter representing the number of available resources, managing exclusive access through P (acquire) and V (release) operations.
Branch prediction
A mechanism that predicts the target of a branch instruction ahead of time so the pipeline is not disrupted when the prediction is correct, preserving throughput. A mispredicted branch triggers a pipeline flush and adds latency, so in real-time embedded control the resulting execution-time variability (jitter) from mispredictions can become a design concern.
Prerequisites: Pipeline processing
Event flag
A synchronization object made up of multiple bits, where each bit represents the occurrence of a specific event. A task can wait until a particular bit pattern is satisfied (a single event, or an AND/OR combination of multiple events), offering more flexibility than a semaphore when synchronization depends on a combination of asynchronous events.
Prerequisites: Semaphore
FTA (Fault Tree Analysis)
A top-down analysis method that places an undesired top event at the apex and decomposes the contributing factors into a tree using logic gates (AND/OR). It is the reverse approach of FMEA, and it is well suited to visualizing combinatorial risks where a serious accident occurs only when multiple failures coincide.
Prerequisites: FMEA (Failure Mode and Effects Analysis)
GPIO (General-Purpose I/O)
A general-purpose digital input/output pin whose direction (input/output), pull-up/pull-down configuration, and other settings can be switched by software through registers. Because it has no fixed dedicated function, it can be freely assigned to a purpose — reading a switch, driving an LED, or controlling a simple external device — making it the most basic I/O mechanism in embedded systems.
Prerequisites: Pull-up resistor
Hard real-time / soft real-time
A classification based on how tolerant a system is to missed deadlines. Hard real-time requirements are strict: even a single missed deadline can cause system failure or an accident (e.g., airbag control). Soft real-time requirements tolerate missed deadlines as mere performance degradation (e.g., video playback). This classification drives the choice of scheduling policy and verification method.
ISO 26262
An international functional-safety standard specific to automotive electrical/electronic systems. Derived from IEC 61508 for the automotive domain, it determines an Automotive Safety Integrity Level (ASIL) A through D based on severity, exposure, and controllability of a hazard, and specifies the development process and verification methods required at each level. ASIL D is the most stringent level.
Related: IEC 61508、Functional safety
Message queue
A FIFO (first-in, first-out) buffering mechanism for passing data between tasks, or between a task and an interrupt handler. The sender enqueues messages and the receiver can block waiting for one to arrive, coupling tasks more loosely than a direct function call and making it well suited to producer-consumer style processing.
Prerequisites: Interrupt Service Routine (ISR)
Nested interrupt
A mechanism that accepts a higher-priority interrupt while a lower-priority interrupt handler is still running, suspending the current handler to service the more urgent one first. It preserves responsiveness to urgent events, but it increases stack consumption and can cause inconsistencies if critical sections within handlers are not designed carefully.
Prerequisites: Critical section
Preemption
A mechanism by which the scheduler forcibly suspends the currently running task and switches to a higher-priority task the moment that task becomes ready. It ensures prompt response to urgent work, but requires careful protection of critical sections so the preempted task is not interrupted while resources are in an inconsistent state.
Prerequisites: Critical section
Priority inversion
A phenomenon in which a high-priority task, while waiting for a shared resource lock held by a low-priority task, keeps losing the CPU to a medium-priority task — so the high-priority task is effectively delayed behind the medium-priority one. It is a serious cause of missed deadlines and must be addressed with priority inheritance or priority ceiling protocols.
Flip-flop
A basic sequential-circuit element that can hold one bit of information. It latches its input in sync with a clock signal and holds the output until the next clock, serving as a building block for registers, counters, and other memory circuits.
Pipeline processing
A technique that divides instruction execution into stages such as fetch, decode, execute, and write-back, processing the stages of multiple instructions concurrently to increase CPU throughput. Branch instructions and similar cases can cause pipeline hazards.
Prerequisites: Write-through / write-back
Related: Instruction pipeline hazard
CPU and clock frequency
The CPU (central processing unit) is the core of a computer, handling computation and control. Clock frequency (measured in Hz) indicates how many signal cycles the CPU can process per second; generally, a higher value indicates faster processing.
Availability rate
The proportion of time a system operates correctly. Availability = MTBF ÷ (MTBF + MTTR); it rises as time-between-failures grows and repair time shrinks. A core availability metric, also used as an agreed SLA target (e.g., 99.9%).
Prerequisites: MTBF (mean time between failures)
Combinational circuit / sequential circuit
A combinational circuit is one whose output depends only on the current inputs (built from gates such as AND/OR/NOT). A sequential circuit contains memory elements such as flip-flops, so its output depends on both current inputs and past internal state. This distinction underlies embedded timing design and state-transition design; sequential circuits require clock-synchronized behavior analysis.
Related: Flip-flop
Instruction pipeline hazard
A disruption in instruction pipelining (a stall or flush) caused when a branch instruction or a data dependency prevents a subsequent instruction from executing correctly. Hazards are classified as structural, data, or control (branch) hazards. In embedded systems they threaten real-time determinism, so branch prediction and instruction reordering are important mitigations.
Prerequisites: Branch prediction
Related: Pipeline processing
Priority inheritance / priority ceiling protocol
Two remedies for priority inversion. Priority inheritance temporarily raises the priority of the low-priority task holding a lock that a high-priority task is waiting for, up to the waiting task's level, so it cannot be preempted by a medium-priority task. The priority ceiling protocol instead pre-assigns each shared resource a ceiling equal to the highest priority among all tasks that might use it, and immediately raises the locking task to that ceiling — a simpler implementation that also prevents deadlock as a side effect.
Related: Priority inversion
Pull-up resistor
A circuit that connects an input pin to the supply voltage through a resistor, holding it at a High level unless something externally pulls it Low. It is used with open-drain or open-collector output devices (such as I2C lines) and to keep an input from floating (an undefined level) when a switch is in its open state.
Rate Monotonic Scheduling (RMS)
A scheduling policy for periodic tasks that statically assigns higher priority to tasks with shorter periods. Among fixed-priority scheduling policies for tasks with known periods and execution times, it is optimal, and the Liu & Layland sufficient condition — total utilization at or below n(2^(1/n)-1) for n tasks — lets designers verify at design time whether deadlines can be met.
Reentrant
A property of a function or routine whereby it behaves correctly even when called concurrently by multiple tasks or interrupt handlers, or re-entered after being interrupted mid-execution, without corrupting shared state. It is achieved by avoiding modification of global or static variables and relying only on local variables, and it is a required property for functions called from both interrupt handlers and multiple tasks.
Related: Interrupt Service Routine (ISR)
SRAM / DRAM
SRAM holds each bit in a flip-flop, giving fast access but a larger cell size, higher cost, and lower density. DRAM stores each bit as charge on a capacitor, requiring periodic refresh, but achieves smaller cell size, lower cost, and higher density. Embedded systems typically use SRAM for caches and fast working memory, and DRAM for large main memory.
Prerequisites: Flip-flop
Task state transition
The set of states a task can occupy under an RTOS (running, ready, waiting/blocked, etc.) and the transitions between them. Only one task occupies the running state at a time; ready tasks wait for the scheduler to select them; and waiting tasks are blocked on an event or resource. Correctly understanding this transition model underlies root-cause analysis of faults such as deadlocks or priority inversion.
Prerequisites: Priority inversion、Real-Time OS (RTOS)
UART (Universal Asynchronous Receiver/Transmitter)
An asynchronous serial communication method in which no clock signal is shared; each device uses its own independent clock and communicates based on a pre-agreed baud rate. Wiring is minimal — just TX and RX — but communication fails if both sides' baud rate settings do not match. It is widely used for debug consoles and simple point-to-point communication.
MTBF (mean time between failures)
For a repairable system, the average operating time from one failure to the next. A larger value means fewer failures and higher reliability. Computed as total operating time ÷ number of failures.
MTTR (mean time to repair)
The average time from a failure until recovery. A smaller value means faster recovery and better maintainability. Computed as total repair time ÷ number of failures; it is part of the denominator in availability = MTBF ÷ (MTBF + MTTR), assessed together with MTBF (mean time between failures) for reliability and maintainability.
Prerequisites: Availability rate、MTBF (mean time between failures)
Bootloader
A small program that runs first immediately after power-on or reset. After performing minimal hardware initialization, it loads the main firmware image, stored in flash memory or similar, into memory and starts its execution. In OTA update scenarios it often also handles switching between old and new firmware images and rolling back on a failed write, making it directly tied to device reliability.
Dynamic Voltage and Frequency Scaling (DVFS)
A power-saving technique that dynamically varies a processor's clock frequency and supply voltage according to workload, delivering the performance needed while curbing power consumption. Since power draw is roughly proportional to the square of voltage and to frequency, lowering both during low-load periods yields a large benefit, making DVFS an important technique in the power design of battery-operated embedded devices.
Prerequisites: CPU and clock frequency
Earliest Deadline First (EDF)
A scheduling policy that dynamically assigns the highest priority to whichever task has the nearest deadline. Unlike the fixed-priority rate-monotonic policy, priorities change at run time under this dynamic-priority scheme. On a single processor it can theoretically achieve schedulability up to 100% utilization, but the trade-off is greater implementation complexity and unpredictable behavior under overload.
Prerequisites: Rate Monotonic Scheduling (RMS)
Secure boot
A mechanism that verifies the digital signature of the bootloader or firmware at startup and allows only legitimate, untampered software to run. Because it refuses to boot even if an attacker has flashed unauthorized firmware, it serves as a foundational embedded-security mechanism for IoT devices with OTA update capability, preventing unauthorized code execution or device takeover.
Prerequisites: Bootloader
Write-through / write-back
Cache write policies. Write-through writes to both the cache and main memory simultaneously, preserving consistency at the cost of higher bus traffic. Write-back writes only to the cache and defers the update to main memory, giving higher speed but risking data loss if power is lost before the write-back occurs. Embedded designers choose between them based on the trade-off between real-time performance and data integrity.