2Memory & storage

• 2.1Memory hierarchy & access

  Covers the trade-offs in the memory hierarchy between fast-but-expensive SRAM and high-capacity DRAM that requires refresh, the relationship between access latency and cost/capacity, and how to choose a memory configuration under the capacity, cost, and power constraints unique to embedded devices.

• 2.2Cache & memory protection

  Covers the two cache-update policies, write-through and write-back, the hit rate that governs performance, the embedded-specific concern of real-time impact (response-time variability caused by cache misses), and the difference between MMU and MPU for protecting address spaces and regions.

• 2.3Non-volatile memory

  Covers the two flagship non-volatile memories that retain data with power removed—NOR flash and NAND flash—and how their uses differ, EEPROM for byte-addressable rewriting, and the embedded-unavoidable write-cycle endurance limit together with wear leveling, the technique that spreads writes to mitigate it.

• 2.4DMA & memory-mapped I/O

  Covers DMA (direct memory access), which transfers data between memory and a device without CPU involvement to offload the CPU, memory-mapped I/O, which treats a peripheral device's registers as part of the memory address space, and bus arbitration, the contention that arises when multiple bus masters share a bus, along with its conflict with real-time behavior.