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Chapter 6 · IoT, functional safety & low power·v1.0.0·Updated 7/10/2026·~17 min

What's changed: Initial version

6.2Low-power design

Key points

Covers sleep and deep sleep modes that halt the CPU to cut power, clock gating that stops the clock to idle circuitry, DVFS that dynamically lowers voltage and frequency to match workload, intermittent operation that stays dormant and wakes only to communicate, and, building on all of these, estimating average current and battery life.

For a battery-powered IoT device, what determines "how many years it can run without a battery change" comes down entirely to average current draw. An embedded designer must make the design decision to draw power only in the instant it is needed and aggressively cut power at all other times, rather than running full-tilt continuously, and must be able to quantify the result as average current and battery life and verify it meets requirements.

6.2.1Sleep/deep sleep and clock gating

  • Sleep stops the CPU clock and halts instruction execution, but retains peripheral circuitry and RAM contents, allowing a swift return when an interrupt occurs. Deep sleep goes further, cutting power supply itself to the CPU and many peripherals. Power consumption is far lower than sleep, but this comes with a trade-off: wake-up takes longer, and RAM contents may be lost.
  • Clock gating is a power-saving technique that individually stops the clock supplied to unused circuit blocks. Even though the circuit itself remains powered, once its clock stops, its switching activity (i.e., dynamic power consumption) drops to nearly zero. Supplying the clock only to the circuits actually needed allows fine-grained power reduction without halting the whole chip.

6.2.2DVFS and intermittent operation

  • DVFS (Dynamic Voltage and Frequency Scaling) dynamically lowers operating voltage and clock frequency when the workload is light, raising them only when the workload is heavy. Because CPU power consumption scales roughly with the square of voltage times frequency, lowering voltage and frequency whenever there is performance headroom yields a substantial power reduction compared to always running at maximum performance.
  • Intermittent operation stays dormant most of the time (e.g., in deep sleep), waking briefly at a predetermined interval (e.g., every 10 seconds) to take a sensor reading and transmit wirelessly, then returning to dormancy. The smaller the fraction of time spent awake (duty cycle), the lower the average current draw, but stretching the wake interval too far trades off data freshness and real-time responsiveness.
Exam point

Most-tested contrasts: "sleep = RAM retained, fast wake-up", "deep sleep = power itself is cut, wake-up is slower and RAM may be lost", "clock gating = stops the clock only to unused circuitry", "DVFS = dynamically controls voltage/frequency to match load (power scales roughly with voltage squared)", and "intermittent operation = the lower the duty cycle, the lower the average current". Be sure to master the average-current formula (sum of each state's current times its duration, divided by the cycle period).

6.2.3Estimating average current and battery life

  • Estimating average current sums, over one cycle of intermittent operation, "each state's (active/sleep) current value times how long that state lasts," then divides by the total cycle duration. Battery life can be approximated by dividing battery capacity (mAh) by the average current (mA), giving the runtime in hours.
  • Example: over a 10-second cycle with 0.1 s active at 20 mA and the remaining 9.9 s asleep at 0.002 mA, average current = (20mA x 0.1s + 0.002mA x 9.9s) / 10s = (2 + 0.0198) / 10 ~= 0.202 mA. With a 1000 mAh battery, battery life = 1000 / 0.202 ~= 4950 hours (about 206 days, roughly 6.8 months). Shortening active time or reducing wake frequency lowers average current and extends battery life.

Suppose a firmware developer must verify whether an environmental sensor node powered by a coin cell (220 mAh capacity) can meet a requirement of running 2 years (about 17,520 hours) without a battery change. Measuring the current design shows a 10-second cycle with 0.1 s active at 20 mA and 9.9 s asleep at 0.002 mA, giving an average current of about 0.202 mA. Battery life comes to only 220mAh / 0.202mA ~= 1089 hours (about 45 days)—far short of the 2-year requirement. The developer first considers lengthening the cycle to reduce wake frequency (lowering the intermittent-operation duty cycle). Stretching the cycle from 10 s to 60 s gives average current = (20mA x 0.1s + 0.002mA x 59.9s) / 60s = (2 + 0.1198) / 60 ~= 0.0353 mA, extending battery life to 220 / 0.0353 ~= 6232 hours (about 260 days)—still short of 2 years. Next, to cut the current drawn during the active period itself, the developer adds DVFS to lower the clock during sensor measurement and wireless transmission according to load, plus clock gating on unused peripherals even during the active window to trim wasted consumption. If this reduces the active-state average current from 20 mA to 8 mA, the average current at a 60-second cycle becomes (8mA x 0.1s + 0.002mA x 59.9s) / 60s ~= 0.01400 mA, extending battery life to 220 / 0.0140 ~= 15714 hours (about 1.79 years). Still slightly short of the 2-year requirement, the developer finally considers adopting deep sleep (cutting the sleep-state current by a further fraction)—this iterative cycle of staged low-power design and numeric verification is what the practice looks like.

TechniqueEffectTrade-off
SleepCPU halted, RAM retainedFast wake-up but limited power savings
Deep sleepPower itself cut, large power savingsSlower wake-up, possible RAM loss
Clock gatingStops clock only to unused circuitryCircuit itself remains powered
DVFSLowers voltage/frequency to match loadPower rises when performance is needed
Intermittent operationLowers duty cycle to cut average currentLonger intervals reduce data freshness
Warning

Trap: "Deep sleep is always superior to sleep, so just switch to it" is wrong—deep sleep takes longer to wake up and may lose RAM contents, so for use cases requiring frequent wake-ups, the wake-up overhead can actually work against you. Also wrong: "battery life is determined by battery capacity alone"—it is determined by average current (a combination of active duration, current draw, and wake frequency), and for the same capacity, life can vary greatly depending on the design.

Sleep/DVFS/duty cycling.
Stretching battery life

6.2.4Section summary

  • Sleep = RAM retained, fast wake-up, deep sleep = power cut, large savings but slower wake-up
  • Clock gating = stops the clock to unused circuitry, DVFS = dynamically controls voltage/frequency to match load
  • Lowering the duty cycle of intermittent operation reduces average current and extends battery life (battery capacity [mAh] / average current [mA] = life [hours])

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Quick check

(just a quick review)

Q1. A coin-cell-powered environmental sensor performs intermittent operation with a 10-second cycle: 0.1 s active (20 mA) and 9.9 s asleep (0.002 mA). Its battery life turns out to be only about 45 days against a 2-year requirement. Which countermeasure is most direct to try first?

Q2. A sensor performs intermittent operation with a 60-second cycle: 0.1 s active (8 mA) and 59.9 s asleep (0.002 mA), powered by a 220 mAh battery. Which value is closest to the resulting battery life?

Q3. An IoT device always runs its CPU at maximum clock and voltage even during light, idle-like measurement processing, resulting in excessive power consumption. Which design most appropriately reduces power to match the actual load?

Check your understandingPractice questions for Chapter 6: IoT, functional safety & low power

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