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Chapter 6 · IoT, functional safety & low power·v1.0.0·Updated 7/10/2026·~17 min

What's changed: Initial version

6.2Low-power design

Key points

Covers sleep and deep sleep modes that halt the CPU to cut power, clock gating that stops the clock to idle circuitry, DVFS that dynamically lowers voltage and frequency to match workload, intermittent operation that stays dormant and wakes only to communicate, and, building on all of these, estimating average current and battery life.

For a battery-powered IoT device, what determines "how many years it can run without a battery change" comes down entirely to average current draw. An embedded designer must make the design decision to draw power only in the instant it is needed and aggressively cut power at all other times, rather than running full-tilt continuously, and must be able to quantify the result as average current and battery life and verify it meets requirements.

6.2.1Sleep/deep sleep and clock gating

  • Sleep stops the CPU clock and halts instruction execution, but retains peripheral circuitry and RAM contents, allowing a swift return when an interrupt occurs. Deep sleep goes further, cutting power supply itself to the CPU and many peripherals. Power consumption is far lower than sleep, but this comes with a trade-off: wake-up takes longer, and RAM contents may be lost.
  • Clock gating is a power-saving technique that individually stops the clock supplied to unused circuit blocks. Even though the circuit itself remains powered, once its clock stops, its switching activity (i.e., dynamic power consumption) drops to nearly zero. Supplying the clock only to the circuits actually needed allows fine-grained power reduction without halting the whole chip.

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