2Computer systems

• 2.1The Processor and Parallel Processing

  Building on the instruction execution cycle from FE/SG, learn the three categories of pipeline hazards (structural, data, control) and how to address them, superscalar execution (issuing multiple instructions at once), and out-of-order execution (reordering instructions). We also cover the SIMD/MIMD classification of parallel processing via multicore CPUs and GPUs, and calculations for pipeline execution time, MIPS, and CPI.

• 2.2Memory and the Storage Hierarchy

  Building on the FE/SG basics of cache and virtual memory, this section works through effective access time and hit-rate calculations precisely and digs deeper into the performance/reliability tradeoff between write-through and write-back. It also covers virtual memory page replacement algorithms (LRU/FIFO), page-fault calculations, and multi-level cache configurations (L1/L2/L3).

• 2.3System Configuration and Virtualization

  Building on the FE/SG coverage of client-server, three-tier web, and clustering, this section goes deeper into virtualization's core component, the hypervisor (bare-metal vs. hosted), and how it differs from the lighter-weight container approach (e.g., Docker). It also covers load-balancing methods (round robin, least connections), the shared-responsibility split across IaaS/PaaS/SaaS, and redundant configurations (dual system vs. duplex system).

• 2.4Performance Evaluation and Reliability

  Building on the FE/SG basics of response time/throughput and availability, this section digs deeper into performance estimation via queueing theory (the M/M/1 model, calculating utilization and average wait time), series/parallel/mixed availability calculations, MTBF/MTTR, RASIS, and capacity management thinking.

• 2.5The OS and Middleware

  Building on the FE/SG basics of task management and mutual exclusion, this section goes deeper into comparing scheduling schemes (round robin, priority, SJF), how semaphores implement mutual exclusion, and the four necessary conditions for deadlock and how to avoid it. It also covers the relationship between virtual memory and process management, the role of middleware (DBMS, application servers, message queues), and OSS licenses (GPL, MIT, etc.).

• 2.6Hardware and Embedded Systems

  Building on the FE/SG basics of logic circuits and flip-flops, this section digs deeper into the design of combinational circuits (half adders/full adders) and sequential circuits, and reading circuits from truth tables. It also covers practical design decisions for IoT devices (sensors/actuators), the responsiveness of a real-time OS (RTOS), and embedded-specific power-saving design (dynamic voltage and frequency scaling, etc.).