2.6Hardware and Embedded Systems

FE/SG asks you to distinguish combinational from sequential circuits. AP goes a step further, requiring the ability to read a concrete circuit (an adder) from its truth table, as well as an understanding of the practical requirements of real-time responsiveness and power efficiency that embedded systems cannot avoid.

2.6.1Half adders and full adders

• A half adder is a combinational circuit that adds two 1-bit inputs and outputs a sum (S) and a carry (C). For inputs A and B, it is realized by the logic expressions S = A XOR B (exclusive OR) and C = A AND B. However, a half adder has the limitation that it cannot accept a carry-in from a lower digit, so it cannot be chained on its own to add numbers with multiple digits.
• A full adder resolves the half adder's limitation: it accepts two 1-bit inputs plus a carry-in (Cin) from a lower digit, producing a sum (S) and a carry-out (Cout) to the next digit. Chaining full adders for however many digits are needed (feeding each Cout into the next digit's Cin) builds a binary adder circuit for numbers of any length. The table above is a full adder's truth table (example S/Cout values for combinations of A, B, and Cin).

Let us verify a full adder's truth table with real numbers. Consider inputs A = 1, B = 1, and a carry-in from a lower digit Cin = 1. Adding these naively in binary: 1 + 1 + 1 = 3 (decimal) = 11 (binary). Binary "11" means the low digit is 1 and the high digit (the carry) is 1, so sum S = 1 and carry-out Cout = 1, matching the last row of the table above (A=1, B=1, Cin=1 gives S=1, Cout=1). Likewise, for A = 1, B = 1, Cin = 0: 1 + 1 + 0 = 2 (decimal) = 10 (binary), giving S = 0, Cout = 1. This match is not a coincidence—the full adder's logic expressions are designed precisely so that the sum of three 1-bit inputs is correctly represented as a 2-digit binary number (S and Cout). Building on this, an 8-bit binary adder can be realized by chaining 8 full adders, with each digit's Cout feeding into the next digit's Cin in sequence (the lowest digit either has its Cin fixed at 0, or uses a half adder instead). Turning to practical IoT device design, many embedded devices run on a real-time OS (RTOS). Whereas a general-purpose OS prioritizes "average throughput," an RTOS prioritizes guaranteeing that processing always completes within a set time (predictable response time) above all else. In automotive airbag control, for instance, "fast on average" is not sufficient for the input from a collision sensor—the requirement is that the actuator (the ignition device) must always fire within a specified time, even in the worst case—and the design philosophy that guarantees this is called hard real-time (use cases that can tolerate some delay are instead called soft real-time). For battery-powered IoT devices, power-saving design—cutting power to unused circuit blocks, or DVFS (Dynamic Voltage and Frequency Scaling), which dynamically lowers clock frequency and voltage according to processing load—becomes a key design factor governing operating time.

2.6.2Section summary

• Half adder = cannot accept a carry-in from a lower digit (S = XOR, C = AND). Full adder = also accepts Cin and can be chained; chaining builds an adder for any number of digits
• Real-time OS (RTOS) prioritizes not average speed but the predictability of response time (hard real-time vs. soft real-time)
• DVFS dynamically adjusts both clock frequency and voltage based on load, as a power-saving technique. IoT devices consist of a sensor (input) plus an actuator (output)