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2.1The Processor
Learn the basic cycle by which a CPU executes instructions (fetch, decode, execute, store), and the registers, pipelining, and CISC/RISC design philosophies that determine its speed. We also cover performance metrics such as clock frequency and MIPS, and how multicore processors and GPUs divide labor, organizing the processor as a whole from a practical perspective.
No matter how cleverly an application is written, it is ultimately the CPU (central processing unit) that executes it. Understanding the steps a CPU takes to process a single instruction, and the ingenuity layered on top to speed those steps up, lets you judge with real grounds why a given configuration is slow or fast.
2.1.1The instruction execution cycle and registers
- The instruction execution cycle is the basic repeating process by which a CPU handles one machine-language instruction: fetch (retrieve the instruction from main memory) -> decode (interpret it) -> execute (perform the operation) -> store (write the result back to a register or main memory).
- A register is an internal CPU storage element that is extremely fast but extremely small in capacity. Besides general-purpose registers holding operands and intermediate results, there are role-specific ones such as the program counter (instruction address register), which holds the address of the next instruction to execute, and the instruction register, which holds the instruction currently being executed. Registers are orders of magnitude faster than main memory, at the cost of holding very little data.
2.1.2Pipelining and CISC/RISC
- Pipelining is a speedup technique that overlaps the stages of the instruction cycle (fetch, decode, execute, store) like an assembly line: while one instruction is being decoded, the next instruction's fetch can already begin, keeping each stage's circuitry busy instead of idle. However, a branch instruction (where the next instruction to run depends on a condition) can cause a pipeline hazard, wasting instructions that were speculatively fetched and hurting performance.
- CISC (Complex Instruction Set Computer) is an instruction-set design with a large, highly capable set of instructions so that a single instruction can accomplish a complex operation. RISC (Reduced Instruction Set Computer) is a design philosophy that narrows the instruction set down to simple ones, aiming for execution close to one clock cycle per instruction; complex operations are built by combining simple instructions, which pairs well with pipelining.
The staples: the instruction execution cycle is fetch -> decode -> execute -> store; pipelining runs stages in parallel for speed, but branch instructions can cause hazards; CISC = a complex, feature-rich instruction set, while RISC = a reduced instruction set that pairs well with pipelining. A classic trap is the oversimplified belief that "raising the clock frequency always increases processing speed proportionally."
Picture an evaluation scenario. A team estimates that "the new CPU's clock frequency is 1.5 times the old model's, so processing speed should also be 1.5 times faster." But real programs are full of branch instructions, whose execution path depends on a condition, so pipelined instructions that were speculatively fetched are often wasted. The more branch-heavy the workload, the less the raw clock-frequency gain translates into actual speedup. Instruction-set differences also matter: many embedded devices and modern high-performance processors use RISC-style designs, maximizing pipeline efficiency by executing a large volume of simple instructions quickly. Traditional general-purpose PC processors, meanwhile, expose a CISC-style instruction set externally but widely use a hybrid implementation that internally decomposes instructions into simpler micro-operations for execution. When discussing performance, the sound practical judgment is to look beyond a single metric like clock frequency and also weigh an effective throughput metric such as MIPS (Million Instructions Per Second) alongside real-workload benchmark measurements.
2.1.3Multicore and GPU
| Category | Strength | Characteristics |
|---|---|---|
| Multicore CPU | Running different sequential tasks in parallel | Has as many independent instruction-execution pipelines as cores |
| GPU | Applying the same simple operation to massive amounts of similar data in parallel | A massively parallel compute device widely used for graphics and AI training |
- A multicore configuration integrates multiple independent CPU cores onto a single chip. Facing heat and power limits on pushing clock frequency ever higher, processor design has shifted toward adding cores and gaining overall throughput through parallel processing. This benefit depends on software being able to split its work across multiple cores (i.e., being parallelized); a purely sequential task does not speed up just because more cores exist.
- A GPU (Graphics Processing Unit) is a processor originally designed for rendering graphics, specialized for carrying out a huge number of simple operations concurrently. Because it excels at applying the same computation repeatedly across massive amounts of data, it is now widely repurposed beyond graphics for machine learning training, which involves enormous volumes of matrix operations.
Trap: "a CPU with a higher clock frequency is always faster for any workload" is wrong—due to pipeline hazards and instruction-set differences, effective performance depends on the workload. Also, "going multicore automatically speeds up simple sequential processing" is wrong—if the software is not parallelized, adding cores does not increase speed. "A GPU is strictly superior to a CPU and suits every kind of processing" is also wrong—GPUs excel at simple operations over large amounts of similar data, while CPUs remain better at complex sequential processing with heavy branching.
2.1.4Section summary
- The instruction execution cycle is fetch -> decode -> execute -> store. Registers are tiny in capacity but the fastest storage. Pipelining overlaps stages but branch instructions can cause hazards
- CISC = a complex, feature-rich instruction set; RISC = a reduced instruction set that pairs well with pipelining. Evaluate effective performance with MIPS and benchmarks, not clock frequency alone
- Multicore pays off only for parallelized software; GPU specializes in simple operations over large amounts of similar data
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Quick check
(just a quick review)Q1. Which is the correct order of the basic steps a CPU takes to process one machine-language instruction?
Q2. A program with many conditional branches ran under pipelining but did not gain as much performance as expected. What is the most likely cause?
Q3. You want to speed up applying the same filter operation repeatedly to a large volume of image data. Which processing device is most suitable?